I design digital hardware and write the low-level software that runs on it, from RTL and chip layout to optimized RISC-V code.
A full JPEG encoder for the 8-core Snitch RISC-V cluster, optimized with stream registers, hardware loops and FP16 SIMD. On a single core it runs 4.4 times faster than the plain C version.
Custom modulo adders (mod 5, 9, 14, 15) taken from VHDL through synthesis and place-and-route at 45 nm and 7 nm.
DES and Triple DES in VHDL, built around a 16-round Feistel datapath with on-the-fly key scheduling.
A web platform for the Region of Attica to manage its bridges, with interactive maps, inspection documents and automatic backups.